| Description |
vi, 118 leaves : illustrations ; 28 cm. |
| Summary |
"This paper describes the organization and failure analysis of various types of binary address decoders. Logical type faults are considered and all possible faulty output patterns, resulting from these faults, are derived. A basic theory is developed, showing that these failure patterns are independent of the decoder size and organization. Digital simulation programs were used as an aid in the development of this theory. Results of the simulation are provided in the appendix"--Abstract, leaf ii. |
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