| Description |
xi, 98 leaves : illustrations ; 29 cm |
| Summary |
"Functional verification of an ASIC has become one of the most challenging tasks due to the increased system complexity and gate count. More than half of the time consumed in development of new ICs and systems is now spent on verification. This work investigates some of the software testing methodologies that can be adopted for efficient verification of VHDL models. The model that is to be verified is a behavioral VHDL model of the 8051 microcontroller that is being developed at the University of Missouri-Rolla. Code coverage technology, black box testing, white box testing and software fault injection are the different software testing methodologies that are used for the verification of this model. Analysis of the model was done using data flow diagrams, state diagrams, program structure charts and program flow graphs. Enough test instructions were included at the appropriate places in the test program to increase the testability and observability of the code. The level of different types of coverage achieved by different test programs while performing verification of the model was investigated. The types of faults that were found by each of the different testing methodologies were investigated and characterized. Test vectors developed for testing this behavioral VHDL model are useful for testing the register transfer level (RTL) model and also to test the final ASIC. Each of the different testing techniques, black box testing, white box testing and fault injection testing, was found to uncover at least one new error that was not exposed by the other two techniques. Most of the errors and much useful information for error correction were obtained during white box testing"--Abstract, leaf iv. |
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