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Theses/Dissertations
Author Bandapati, Satish Kumar, 1980-

Title Design and characterization of asynchronous delay-insensitive arithmetic components using NULL conventional logic / by Satish Kumar Bandapati.

Published ©2003.
LOCATION CALL # STATUS
 MST DEPOSITORY  THESIS T 8434/8461  MICROFILM    NOT CHECKED OUT
 MST Thesis  THESIS T 8439    NOT CHECKED OUT
Description x, 67 leaves : illustrations ; 28 cm.
Summary "This thesis focuses on design and characterization of arithemetic circuits, such as multipliers and ALUs, using the asynchronous delay-insensitive NULL Convention Logic (NCL) paradigm. This work helps to build a library of reusable components to aid in the integration of asynchronous design paradigms, like NCL, into the semiconductor design industry."--Abstract, p. iii.
Notes Vita.
Includes bibliographical references (pages 65-66).
M.S. University of Missouri--Rolla 2003.
Subjects Computer arithmetic and logic units.
Computer programming.
Logic circuits.
Other Titles MST thesis. Computer Engineering (M.S., 2003).
Additional Keywords NULL Convention Logic (NCL)
OCLC/WorldCat Number 55232239
Author Bandapati, Satish Kumar, 1980-
Title Design and characterization of asynchronous delay-insensitive arithmetic components using NULL conventional logic / by Satish Kumar Bandapati.
Subjects Computer arithmetic and logic units.
Computer programming.
Logic circuits.
Additional Keywords NULL Convention Logic (NCL)
Other Titles MST thesis. Computer Engineering (M.S., 2003).
Permanent Link
http://merlin.lib.umsystem.edu:80/record=b5089517~S5