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Theses/Dissertations
Author Mallepalli, Samarsen Reddy, 1981-

Title Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplication / by Samarsen Reddy Mallepalli.

Published ©2007.
LOCATION CALL # STATUS
 MST DEPOSITORY  THESIS T 9252/9277  MICROFILM    NOT CHECKED OUT
 MST Thesis  THESIS T 9265    NOT CHECKED OUT
Description ix, 68 leaves : illustrations ; 28 cm.
Summary "This thesis focuses on designing generic quad-rail arithmetic circuits, such as signed and unsigned multipliers and Multiply and Accumulate (MAC) units, using the asynchronous delay-insensitive NULL Convention Logic (NCL) paradigm. This work helps to build a library of reusable components to be used for automated NCL circuit synthesis, which will aid in the integration of asynchronous design paradigms into the semiconductor industry"--Abstract, leaf iii.
Notes Vita.
Includes bibliographical references (leaves 66-67).
M.S. University of Missouri--Rolla 2007.
Subjects Asynchronous circuits -- Design and construction.
Logic circuits -- Design and construction.
Electronic circuit design.
Other Titles MST thesis. Computer Engineering (M.S., 2007).
Additional Keywords NULL Convention Logic.
OCLC/WorldCat Number 233708544
Author Mallepalli, Samarsen Reddy, 1981-
Title Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplication / by Samarsen Reddy Mallepalli.
Subjects Asynchronous circuits -- Design and construction.
Logic circuits -- Design and construction.
Electronic circuit design.
Additional Keywords NULL Convention Logic.
Other Titles MST thesis. Computer Engineering (M.S., 2007).
Permanent Link
http://merlin.lib.umsystem.edu:80/record=b6400724~S5