Add to My Lists Save to Folder MARC Display Another Search Search
MOBIUS
     
Theses/Dissertations
Author Parameswaran Nair, Ravi Sankar, 1983-

Title Delay-insensitive ternary logic (DITL) / by Ravi Sankar Parameswaran Nair.

Published ©2007.
LOCATION CALL # STATUS
 MST DEPOSITORY  THESIS T 9252/9277  MICROFILM    NOT CHECKED OUT
 MST Thesis  THESIS T 9271    NOT CHECKED OUT
Description viii, 57 leaves : illustrations ; 28 cm.
Summary "This thesis focuses on development of a Single Rail Ternary Voltage Delay-Insensitive paradigm called Delay-Insensitive Ternary Logic (DITL), which is based on NULL Convention Logic (NCL). Single rail asynchronous logic has potential advantages over Dual-Rail logic such as reduction of Power and Interconnect as well as Logic Area. The DITL concept is developed in steps of individual circuit components. These components are designed at the transistor level and are connected together to form a registered pipeline system. Some variations in pipeline design are also investigated"--Abstract, leaf iii.
Notes Vita.
Includes bibliographical references (leaves 55-56).
M.S. University of Missouri--Rolla 2007.
Subjects Asynchronous circuits -- Design and construction.
Logic circuits -- Design and construction.
Electronic circuit design.
Other Titles Delay insensitive ternary logic (DITL)
MST thesis. Computer Engineering (M.S., 2007).
Additional Keywords NULL Convention Logic.
OCLC/WorldCat Number 233832330
Author Parameswaran Nair, Ravi Sankar, 1983-
Title Delay-insensitive ternary logic (DITL) / by Ravi Sankar Parameswaran Nair.
Subjects Asynchronous circuits -- Design and construction.
Logic circuits -- Design and construction.
Electronic circuit design.
Additional Keywords NULL Convention Logic.
Other Titles Delay insensitive ternary logic (DITL)
MST thesis. Computer Engineering (M.S., 2007).
Permanent Link
http://merlin.lib.umsystem.edu:80/record=b6401249~S5